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$C\!\!-\!\!Lock$ : Energy Efficient Synchronization for Embedded Multicore Systems., , , , , , и . IEEE Trans. Computers, 63 (8): 1962-1974 (2014)Latency-Aware Bus Arbitration for Real-Time Embedded Systems., , , и . IEICE Trans. Inf. Syst., 90-D (3): 676-679 (2007)Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches., , и . ASP-DAC, стр. 583-588. IEEE, (2008)Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems., , , , и . ASP-DAC, стр. 159-164. IEEE Computer Society, (2007)Partial Connection-Aware Topology Synthesis for On-Chip Cascaded Crossbar Network., , и . IEEE Trans. Computers, 61 (1): 73-86 (2012)Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network., , и . DATE, стр. 1390-1395. IEEE Computer Society, (2010)Asymmetric DRAM synthesis for heterogeneous chip multiprocessors in 3D-stacked architecture., , и . ICCAD, стр. 73-80. ACM, (2012)Jitter-Conscious Bus Arbitration Scheme for Real-Time Systems., , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (2): 643-647 (2009)Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis., , и . IEEE Trans. Computers, 63 (6): 1434-1445 (2014)Topology Synthesis of Cascaded Crossbar Switches., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (6): 926-930 (2009)