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Design of a universal logic block for fault-tolerant realization of any logic operation in trapped-ion quantum circuits., , , и . Quantum Inf. Process., 13 (5): 1267-1299 (2014)Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework., , и . DAC, стр. 107:1-107:6. ACM, (2016)Reversible logic synthesis of k-input, m-output lookup tables., , и . DATE, стр. 1235-1240. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A placement algorithm for superconducting logic circuits based on cell grouping and super-cell placement., , и . DATE, стр. 1465-1468. IEEE, (2018)A thermally-aware energy minimization methodology for global interconnects., , , и . DATE, стр. 1213-1218. IEEE, (2017)A Less Biased Evaluation of Out-of-distribution Sample Detectors., , и . BMVC, стр. 3. BMVA Press, (2019)Optimizing the Operating Voltage of Tunnel FET-Based SRAM Arrays Equipped with Read/Write Assist Circuitry., , и . ACM Great Lakes Symposium on VLSI, стр. 415-420. ACM, (2016)Low write-energy STT-MRAMs using FinFET-based access transistors., , и . ICCD, стр. 374-379. IEEE Computer Society, (2014)Cofactor Sharing for Reversible Logic Synthesis., , и . ACM J. Emerg. Technol. Comput. Syst., 11 (2): 14:1-14:21 (2014)A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell., , и . ISQED, стр. 280-285. IEEE, (2018)