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A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications.

, , , , , , , , , , , , , , , , , , , , , , , , , , , и . DAC, стр. 47:1-47:6. ACM, (2017)

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Peter Ellguth IAB Nürnberg

Martin Ellguth

Jennifer Sara Ellguth

Uta Georgi

Herbert George

 

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Low power design of the X-GOLD® SDR 20 baseband processor., , , , , , , и . DATE, стр. 792-793. IEEE Computer Society, (2010)Hardware Implementation of an OPC UA Server for Industrial Field Devices., , , , , , , , , и 6 other автор(ы). CoRR, (2021)Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , и 10 other автор(ы). ISCAS, стр. 1. IEEE, (2017)A low-power cell-based-design multi-port register file in 65nm CMOS technology., , , и . ISCAS, стр. 313-316. IEEE, (2010)Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS., , , , , , , , и . VLSI-SoC, стр. 155-158. IEEE, (2019)Dynamic voltage and frequency scaling for neuromorphic many-core systems., , , , , , , , , и 9 other автор(ы). ISCAS, стр. 1-4. IEEE, (2017)A power management architecture for fast per-core DVFS in heterogeneous MPSoCs., , , , , и . ISCAS, стр. 261-264. IEEE, (2012)Dynamic Power Management for Neuromorphic Many-Core Systems., , , , , , , , , и 5 other автор(ы). CoRR, (2019)The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing., , , , , , , , , и 8 other автор(ы). CoRR, (2021)A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (11): 835-839 (2014)