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Disambiguation of "Chaturvedi, Nitin"

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An FPGA Based Hardware Accelerator for Classification of Handwritten Digits.

, , , and . ISDA (1), volume 940 of Advances in Intelligent Systems and Computing, page 945-954. Springer, (2018)

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Snigdha Chaturvedi

Nidhi Chaturvedi

Sirin Nitinawarat

Anuhar Chaturvedi

Namit Chaturvedi

 

Other publications of authors with the same name

An FPGA Based Hardware Accelerator for Classification of Handwritten Digits., , , and . ISDA (1), volume 940 of Advances in Intelligent Systems and Computing, page 945-954. Springer, (2018)A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications., , , and . Integr., (2019)Twin-Coupled Sense Amplifier to improve margin in 1T-1MTJ based MRAM array., , , and . VDAT, page 1-4. IEEE, (2020)A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications., and . VDAT, volume 1066 of Communications in Computer and Information Science, page 553-564. Springer, (2019)Drone-MAP: A Novel Authentication Scheme for Drone-Assisted 5G Networks., , , and . INFOCOM Workshops, page 1-6. IEEE, (2021)Design of a Programmable Delay Line with On-Chip Calibration to Achieve Immunity Against Process Variations., , , and . VDAT, volume 1687 of Communications in Computer and Information Science, page 408-419. Springer, (2022)An adaptive migration-replication scheme (AMR) for shared cache in chip multiprocessors., , and . J. Supercomput., 71 (10): 3904-3933 (2015)Design of an MTJ/CMOS-Based Asynchronous System for Ultra-Low Power Energy Autonomous Applications., , , , and . J. Circuits Syst. Comput., 30 (4): 2150058:1-2150058:14 (2021)Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher., , , , , , , and . J. Real Time Image Process., 21 (2): 32 (April 2024)An efficient adaptive block pinning for multicore architectures., and . Microprocess. Microsystems, 39 (3): 181-188 (2015)