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Design methodology of embedded DRAM with virtual-socket architecture., , , , , , , and . IEEE J. Solid State Circuits, 36 (1): 46-54 (2001)A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning method for DLL replica., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 35 (11): 1680-1689 (2000)A Low Power Embedded DRAM Macro for Battery-Operated LSIs., , , , , , , , , and 2 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2991-3000 (2003)A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 88-C (10): 2020-2027 (2005)13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM., , , , , , and . ISSCC, page 240-241. IEEE, (2014)A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2671-2680 (2013)Design methodology of the embedded DRAM with the virtual socket architecture., , , , and . CICC, page 271-274. IEEE, (2000)