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Disambiguation of "Watanabe, Naoya"

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A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2671-2680 (2013)

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Wataru Watanabe

Naoya Koseki

Rie Watanabe

Norihiro Watanabe

Shigeo Watanabe

 

Other publications of authors with the same name

Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits., , , , , and . Microelectron. Reliab., (2017)Thermal Stress Comparison of Annular-Trench-Isolated (ATI) TSV with Cu and Solder Core., , , , and . 3DIC, page 1-4. IEEE, (2019)Network Testing for Digital Data Networks., , , , , , and . ICC, page 588-592. IEEE, (1986)A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 88-C (10): 2020-2027 (2005)A 90-MHz 16-Mb system integrated memory with direct interface to CPU., , , , , , , and . IEEE J. Solid State Circuits, 31 (4): 537-545 (1996)13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM., , , , , , and . ISSCC, page 240-241. IEEE, (2014)Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs., , , , , , , , and . 3DIC, page 1-4. IEEE, (2019)Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices., , , , , , , , and . IEEE J. Solid State Circuits, 55 (10): 2747-2755 (2020)Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration., , , , , and . 3DIC, page 1-4. IEEE, (2014)Validation of TSV thermo-mechanical simulation by stress measurement., , , , and . Microelectron. Reliab., (2016)