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SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET.

, , , , and . Microelectron. Reliab., 54 (4): 738-745 (2014)

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All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator., , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 90-94 (2014)Optimization of FinFET-Based Gain Cells for Low Power Sub-V T Embedded DRAMs., , , and . J. Low Power Electron., 14 (2): 236-243 (2018)Novel redundant logic design for noisy low voltage scenarios., , , and . LASCAS, page 1-4. IEEE, (2013)High level spectral-based analysis of power consumption in DSPs systems., , and . ISCAS, IEEE, (2006)PVTA Tolerant Self-adaptive Clock Generation Architecture., , and . PATMOS, volume 7606 of Lecture Notes in Computer Science, page 142-154. Springer, (2012)An automotive case study on the limits of approximation for object detection., , , , , , , , , and 2 other author(s). J. Syst. Archit., (2023)Variability Influence on FinFET-Based On-Chip Memory Data Paths., , , and . J. Low Power Electron., 11 (2): 250-255 (2015)SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET., , , , and . Microelectron. Reliab., 54 (4): 738-745 (2014)Analysis of delay mismatching of digital circuits caused by common environmental fluctuations., , , and . ISCAS, page 2585-2588. IEEE, (2011)New redundant logic design concept for high noise and low voltage scenarios., , , , , and . Microelectron. J., 42 (12): 1359-1369 (2011)