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Disambiguation of "Ho, Ron"

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Digitally-assisted analog circuits for a 10 Gbps, 395 fJ/b optical receiver in 40 nm CMOS.

, , , , , , , , , , , and . A-SSCC, page 29-32. IEEE, (2011)

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Shlomo Ron

Ron Achterrath

Ron Dietrich

Ron Sebastian

Ron Bershan

 

Other publications of authors with the same name

Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-μm CMOS., , , , , , and . IEEE J. Solid State Circuits, 40 (1): 261-275 (2005)Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference., , , and . IEEE J. Solid State Circuits, 44 (1): 3-6 (2009)High Speed and Low Energy Capacitively Driven On-Chip Wires., , , , , , and . IEEE J. Solid State Circuits, 43 (1): 52-60 (2008)Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication., , , , , , , , , and 4 other author(s). ISSCC, page 368-609. IEEE, (2007)A micro-architectural analysis of switched photonic multi-chip interconnects., , , , , , , and . ISCA, page 153-164. IEEE Computer Society, (2012)Optical Interconnects for Present and Future High-Performance Computing Systems., , , , , and . Hot Interconnects, page 175-177. IEEE Computer Society, (2008)Optical Interconnect for High-End Computer Systems., , , , , , , , , and 1 other author(s). IEEE Des. Test Comput., 27 (4): 10-19 (2010)Computer Systems Based on Silicon Photonic Interconnects., , , , , , , , and . Proc. IEEE, 97 (7): 1337-1361 (2009)10-Gbps, 5.3-mW Optical Transmitter and Receiver Circuits in 40-nm CMOS., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 47 (9): 2049-2067 (2012)Low-power SRAM design using half-swing pulse-mode techniques., , , , , , , , and . IEEE J. Solid State Circuits, 33 (11): 1659-1671 (1998)