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Architectural evaluation of 3D stacked RRAM caches.

, и . 3DIC, стр. 1-4. IEEE, (2009)

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J. D. Lewis-Williams

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Catharine Janna Lewis

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An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth., , , и . HPCA, стр. 1-12. IEEE Computer Society, (2010)Design for pre-bond testability in 3D integrated circuits.. Georgia Institute of Technology, Atlanta, GA, USA, (2012)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/45756).A scanisland based design enabling prebond testability in die-stacked microprocessors., и . ITC, стр. 1-8. IEEE Computer Society, (2007)High Performance Non-blocking Switch Design in 3D Die-Stacking Technology., , и . ISVLSI, стр. 25-30. IEEE Computer Society, (2009)Architectural evaluation of 3D stacked RRAM caches., и . 3DIC, стр. 1-4. IEEE, (2009)Testing Circuit-Partitioned 3D IC Designs., и . ISVLSI, стр. 139-144. IEEE Computer Society, (2009)