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FPGA Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process: Methodology, Metrics, Tools, and Results.

, , , , , , and . IACR Cryptol. ePrint Arch., (2020)

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Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design., , , , , , and . FPL, page 397-403. IEEE, (2019)FPGA Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process: Methodology, Metrics, Tools, and Results., , , , , , and . IACR Cryptol. ePrint Arch., (2020)Face-off Between the CAESAR Lightweight Finalists: ACORN vs. Ascon., , , and . FPT, page 330-333. IEEE, (2018)Comparison of hardware and software implementations of selected lightweight block ciphers., , , , and . FPL, page 1-4. IEEE, (2017)COMA: Communication and Obfuscation Management Architecture., , , , , , , and . RAID, page 181-195. USENIX Association, (2019)Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security., , , , and . ACM Great Lakes Symposium on VLSI, page 229-234. ACM, (2021)Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design., , , , , , , , and . CoRR, (2019)Minerva: Automated hardware optimization tool., , , and . ReConFig, page 1-8. IEEE, (2017)A universal hardware API for authenticated ciphers., , , , , and . ReConFig, page 1-8. IEEE, (2015)Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign., , , and . PQCrypto, volume 11505 of Lecture Notes in Computer Science, page 23-43. Springer, (2019)