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Generic Systolic Array for Run-Time Scalable Cores.

, , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 4-16. Springer, (2010)

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Flexible Core Reallocation for Virtex II Structures., , , and . ERSA, page 189-195. CSREA Press, (2005)Partial Reconfiguration for Core Reallocation and Flexible Communications., , and . ReCoSoC, page 91-97. Univ. Montpellier II, (2006)A Fast Emulation-Based NoC Prototyping Framework., , , and . ReConFig, page 211-216. IEEE Computer Society, (2008)Generic Systolic Array for Run-Time Scalable Cores., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 4-16. Springer, (2010)Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems., , , and . FPL, page 1-4. IEEE, (2006)Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs., , , and . IEEE International Workshop on Rapid System Prototyping, page 77-83. IEEE Computer Society, (2005)Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management., , and . ISCAS, page 873-876. IEEE, (2007)Reconfigurable Networks on Chip: DRNoC architecture., , and . J. Syst. Archit., 56 (7): 293-302 (2010)Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs., , , and . FPL, page 70-76. IEEE Computer Society, (2010)