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Disambiguation of "de la Torre, Eduardo"

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Partial Reconfiguration for Core Reallocation and Flexible Communications.

, , and . ReCoSoC, page 91-97. Univ. Montpellier II, (2006)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Martino La Torre

Hector la Torre

Luis La Torre

Silvia Eunice Gutiérrez de la Torre Julius-Maximilians-Universität Würzburg

Eduardo La Riega

 

Other publications of authors with the same name

Message from the chairs., , , and . ReCoSoC, page 1. IEEE, (2015)A dynamic communication strategy for the distributed ATPG system DPLATON., , , and . EURO-DAC, page 271-276. IEEE Computer Society, (1993)Execution modeling in self-aware FPGA-based architectures for efficient resource management., , , , , and . ReCoSoC, page 1-8. IEEE, (2015)Introduction to the Special Section on FPGAs Technology and Applications., , and . Comput. Electr. Eng., (2016)Accelerating the evolution of a systolic array-based evolvable hardware system., and . Microprocess. Microsystems, (2018)Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion., , , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 1057-1061. Springer, (2004)Run-Time Reconfigurable MPSoC-Based On-Board Processor for Vision-Based Space Navigation., , , , , , and . IEEE Access, (2020)Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing., , , , , and . IEEE Trans. Computers, 62 (8): 1481-1493 (2013)Automatic generation of identical routing pairs for FPGA implemented DPL logic., , , and . ReConFig, page 1-6. IEEE, (2012)Generic Systolic Array for Run-Time Scalable Cores., , , and . ARC, volume 5992 of Lecture Notes in Computer Science, page 4-16. Springer, (2010)