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Disambiguation of "Kurose, Daisuke"

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Correction to Ä 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 48 (6): 1540 (2013)

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Daisuke Yoshida

Daisuke Shibata

Daisuke Akimoto

Daisuke Shimizu

Daisuke Mashima

 

Other publications of authors with the same name

28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique., , , , , , , , and . ISSCC, page 478-479. IEEE, (2017)A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters., , , , and . CICC, page 501-504. IEEE, (2006)Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2575-2586 (2019)A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (2): 557-560 (2008)Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design., , , and . IEICE Electron. Express, 1 (3): 63-68 (2004)55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers., , , , and . IEICE Trans. Electron., 91-C (6): 887-893 (2008)A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter., , , , and . IEICE Electron. Express, 2 (15): 429-433 (2005)A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique., , , , , , , , , and 17 other author(s). ISSCC, page 92-94. IEEE, (2018)A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS., , , , , , , , , and 8 other author(s). VLSIC, page 74-75. IEEE, (2012)A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC., , , and . ISCAS, page 1151-1154. IEEE, (2014)