( en | de | ru )

 

Disambiguation of "Tsubouchi, Yuta"

Author of the publication

copydeleteadd this publication to your clipboard
Correction to Ä 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".

, , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 48 (6): 1540 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yuta Toriyama

 

Other publications of authors with the same name

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (5): 1517-1526 (2022)A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR., , , , , , , , , and . ESSCIRC, page 505-508. IEEE, (2022)A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 2 other author(s). ISSCC, page 478-480. IEEE, (2019)Correction to Ä 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication"., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 48 (6): 1540 (2013)A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication., , , , , , , , , and 4 other author(s). ISSCC, page 266-268. IEEE, (2012)A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , and . VLSI Circuits, page 149-150. IEEE, (2018)A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems., , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1086-1095 (2019)A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOS., , , , , , and . ESSCIRC, page 343-346. IEEE, (2011)