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1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Network.

, , , , , , , , and . Adv. Intell. Syst., (June 2023)

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Pulse-Width Modulation Neuron Implemented by Single Positive-Feedback Device., , , , and . CoRR, (2021)Short- and Long-Term Memory Based on a Floating-Gate IGZO Synaptic Transistor., , , , , , , , , and . IEEE Access, (2023)Adaptive Learning Rule for Hardware-based Deep Neural Networks Using Electronic Synapse Devices., , , , , , and . CoRR, (2017)Review of candidate devices for neuromorphic applications., , , , , , , , , and 3 other author(s). ESSDERC, page 22-27. IEEE, (2019)A Spiking Neural Network with a Global Self-Controller for Unsupervised Learning Based on Spike-Timing-Dependent Plasticity Using Flash Memory Synaptic Devices., , , , , , and . IJCNN, page 1-7. IEEE, (2019)Si-Based Dual-Gate Field-Effect Transistor Array for Low-Power On-Chip Trainable Hardware Neural Networks., , , , , , , , and . Adv. Intell. Syst., (January 2024)Improvement of the Symmetry and Linearity of Synaptic Weight Update by Combining the InGaZnO Synaptic Transistor and Memristor., , , , , , , , , and 2 other author(s). IEEE Access, (2024)On-chip trainable hardware-based deep Q-networks approximating a backpropagation algorithm., , , , , , , , , and . Neural Comput. Appl., 33 (15): 9391-9402 (2021)Investigation of Neural Networks Using Synapse Arrays Based on Gated Schottky Diodes., , , , , and . IJCNN, page 1-8. IEEE, (2019)Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems., , , , , , , , and . IEEE Access, (2020)