( en | de | ru )

 

Disambiguation of "Pan, David Z."

Author of the publication

copydeleteadd this publication to your clipboard
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.

, , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (11): 3064-3075 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

David Tse-chien Pan

Z Taufig

Petra Pan

Xiaoqing Pan

Alexey Pan

 

Other publications of authors with the same name

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier., , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2564-2574 (September 2023)A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 55 (12): 3248-3259 (2020)An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback., , and . IEEE J. Solid State Circuits, 55 (5): 1337-1350 (2020)Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (9): 1613-1626 (2018)Light in AI: Toward Efficient Neurocomputing With Optical Neural Networks - A Tutorial., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (6): 2581-2585 (2022)PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (1): 141-150 (January 2024)Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 905-917 (2013)Subresolution Assist Feature Generation With Supervised Data Learning., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (6): 1225-1236 (2018)BOB-router: A new buffering-aware global router with over-the-block routing resources optimization., , and . ASP-DAC, page 513-518. IEEE, (2014)Self-aligned double patterning layout decomposition with complementary e-beam lithography., , and . ASP-DAC, page 143-148. IEEE, (2014)