Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Parallelizing SRAM arrays with customized bit-cell for binary neural networks.

R. Liu, X. Peng, X. Sun, W. Khwa, X. Si, J. Chen, J. Li, M. Chang, and S. Yu. DAC, page 21:1-21:6. ACM, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jia Chen

Jing Chen

Other publications of authors with the same name

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors.Y. Chiu, Z. Zhang, J. Chen, X. Si, R. Liu, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei and 8 other author(s). IEEE J. Solid State Circuits, 55 (10): 2790-2801 (2020)A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.X. Si, R. Liu, S. Yu, R. Liu, C. Hsieh, K. Tang, Q. Li, M. Chang, J. Chen, Y. Tu and 6 other author(s). IEEE J. Solid State Circuits, 55 (1): 189-202 (2020)A 20MS/s buck/boost supply modulator for envelope tracking applications with direct digital interface.S. Yang, C. Wey, K. Chen, Y. Lin, J. Chen, T. Tsai, and C. Lee. A-SSCC, page 73-76. IEEE, (2014)Parallelizing SRAM arrays with customized bit-cell for binary neural networks.R. Liu, X. Peng, X. Sun, W. Khwa, X. Si, J. Chen, J. Li, M. Chang, and S. Yu. DAC, page 21:1-21:6. ACM, (2018)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors.Z. Zhang, J. Chen, X. Si, Y. Tu, J. Su, W. Huang, J. Wang, W. Wei, Y. Chiu, J. Hong and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor using 16 Computing-in-Memory SRAM Macros in 65nm CMOS.R. Guo, Y. Liu, S. Zheng, S. Wu, P. Ouyang, W. Khwa, X. Chen, J. Chen, X. Li, L. Liu and 3 other author(s). VLSI Circuits, page 120-. IEEE, (2019)A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.X. Si, W. Khwa, J. Chen, J. Li, X. Sun, R. Liu, S. Yu, H. Yamauchi, Q. Li, and M. Chang. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (11): 4172-4185 (2019)A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.W. Khwa, J. Chen, J. Li, X. Si, E. Yang, X. Sun, R. Liu, P. Chen, Q. Li, S. Yu and 1 other author(s). ISSCC, page 496-498. IEEE, (2018)A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.X. Si, J. Chen, Y. Tu, W. Huang, J. Wang, Y. Chiu, W. Wei, S. Wu, X. Sun, R. Liu and 6 other author(s). ISSCC, page 396-398. IEEE, (2019)

BibSonomy

Disambiguation of "Chen, Jia-Jing"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Parallelizing SRAM arrays with customized bit-cell for binary neural networks.

Please choose a person to relate this publication to

Jia Chen

Jia Chen

Jing Chen

Jing Chen

Jing Chen

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chen, Jia-Jing"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Parallelizing SRAM arrays with customized bit-cell for binary neural networks.

Please choose a person to relate this publication to

Jia Chen

Jia Chen

Jing Chen

Jing Chen

Jing Chen

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Parallelizing SRAM arrays with customized bit-cell for binary neural networks.