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Parallelizing SRAM arrays with customized bit-cell for binary neural networks.

, , , , , , , , and . DAC, page 21:1-21:6. ACM, (2018)

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A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 58 (3): 877-892 (March 2023)A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors., , , , , , , , , and 6 other author(s). A-SSCC, page 217-218. IEEE, (2019)Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits., , , , and . MCSoC, page 160-165. IEEE, (2023)14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS., , , , , , , , and . ISSCC, page 256-258. IEEE, (2024)16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips., , , , , , , , , and 11 other author(s). ISSCC, page 250-252. IEEE, (2021)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips., , , , , , , , , and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs., , , , , , , , , and 13 other author(s). ISSCC, page 570-572. IEEE, (2024)A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model., , , , and . APCCAS, page 524-527. IEEE, (2022)A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference., , , , , , , , , and 2 other author(s). ISSCC, page 500-501. IEEE, (2023)