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Resistive memory device requirements for a neural algorithm accelerator., , , , , , , and . IJCNN, page 929-938. IEEE, (2016)Research Challenges for Energy-Efficient Computing in Automated Vehicles., , , , , , , , , and 5 other author(s). Computer, 56 (3): 47-58 (March 2023)High-Speed CMOS-Free Purely Spintronic Asynchronous Recurrent Neural Network., , , , , , , , , and 1 other author(s). CoRR, (2021)Process Variation Model and Analysis for Domain Wall-Magnetic Tunnel Junction Logic., , , , , , and . ISCAS, page 1-5. IEEE, (2020)Analog Neural Network Inference Accuracy in One-Selector One-Resistor Memory Arrays., , , , , , , , and . ICRC, page 7-12. IEEE, (2022)PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM., , , , , , , , , and . CoRR, (2019)Unsupervised Competitive Hardware Learning Rule for Spintronic Clustering Architecture., , , , , , , and . CoRR, (2020)An Analog Preconditioner for Solving Linear Systems., , , , , , , , and . HPCA, page 761-774. IEEE, (2021)An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory., , , , , , , , , and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 69 (4): 1480-1493 (2022)Physical Compact Model for Three-Terminal SONOS Synaptic Circuit Element., , , and . Adv. Intell. Syst., (2022)