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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 8 (1): 86-101 (2018)Tunnel-FET Switching Is Governed by Non-Lorentzian Spectral Line Shape., , , , , and . Proc. IEEE, 108 (8): 1235-1244 (2020)Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator., , , , , , , , and . ICRC, page 1-10. IEEE, (2017)Resistive memory device requirements for a neural algorithm accelerator., , , , , , , and . IJCNN, page 929-938. IEEE, (2016)An out-of-distribution discriminator based on Bayesian neural network epistemic uncertainty., , , , , and . CoRR, (2022)Analog Neural Network Inference Accuracy in One-Selector One-Resistor Memory Arrays., , , , , , , , and . ICRC, page 7-12. IEEE, (2022)PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM., , , , , , , , , and . CoRR, (2019)An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory., , , , , , , , , and 2 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 69 (4): 1480-1493 (2022)An Analog Preconditioner for Solving Linear Systems., , , , , , , , and . HPCA, page 761-774. IEEE, (2021)ATHENA: Enabling Codesign for Next-Generation AI/ML Architectures., , , , , , , and . ICRC, page 13-23. IEEE, (2022)