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Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.

, , , , and . VLSI Signal Processing, 46 (2-3): 133-151 (2007)

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Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (5): 1379-1383 (2005)Differential Value Encoding for Delay Insensitive Handshake Protocol., , , and . IEICE Trans. Inf. Syst., 88-D (7): 1437-1444 (2005)A Pilot Symbol Pattern Enabling Data Recovery Without Side Information in PTS-Based OFDM Systems., , , and . TBC, 57 (2): 307-312 (2011)High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion., , , , , and . ACM Great Lakes Symposium on VLSI, page 152-155. ACM, (2005)Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion., , , , , and . IEICE Trans. Electron., 88-C (12): 2395-2399 (2005)A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic., and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 691-700. Springer, (2004)Design of an Asynchronous Switch Based on Butterfly Fat-Tree for Network-on-Chip Applications., , and . PCM (2), volume 3768 of Lecture Notes in Computer Science, page 538-549. Springer, (2005)Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions., , , , and . VLSI Signal Processing, 46 (2-3): 133-151 (2007)Low Complexity Data Decoding for SLM-Based OFDM Systems without Side Information., , and . IEEE Communications Letters, 15 (6): 611-613 (2011)Asynchronous Reorder Buffer for Asynchronous On-Chip Bus., and . IEICE Trans. Electron., 88-C (12): 2391-2394 (2005)