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A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.

Z. Zhang, J. Jiang, Y. Zhu, Q. Wang, Z. Mao, and N. Jing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (7): 2094-2106 (2022)

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Zhigang Shen

Zhigang Zhang

Zhigang Gao

Zhigang Zhang

Other publications of authors with the same name

Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code.J. Guo, L. Xiao, Z. Mao, and Q. Zhao. IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 127-135 (2014)Pareto based Multi-objective Mapping IP Cores onto NoC Architectures.W. Zhou, Y. Zhang, and Z. Mao. APCCAS, page 331-334. IEEE, (2006)Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit.L. Li, L. Xiao, J. Li, H. Liu, and Z. Mao. ASICON, page 1-4. IEEE, (2019)Mapping Long-Term Spatiotemporal Dynamics of Pen Aquaculture in a Shallow Lake: Less Aquaculture Coming along Better Water Quality.J. Luo, R. Pu, R. Ma, X. Wang, X. Lai, Z. Mao, L. Zhang, Z. Peng, and Z. Sun. Remote. Sens., 12 (11): 1866 (2020)Automatic Detection for Acromegaly Using Hand Photographs: A Deep-Learning Approach.C. Duan, W. Chen, S. Yao, Z. Mao, Z. Wang, B. Hu, H. Jiao, D. Zhu, Y. Zhu, and H. Wang. IEEE Access, (2021)Synergistic Effect of BTI and Process Variations on the Soft Error Rate Estimation in Digital Circuits.L. Li, L. Xiao, H. Liu, and Z. Mao. IEEE Access, (2022)An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs.S. Li, Q. Wang, J. Jiang, W. Sheng, N. Jing, and Z. Mao. IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1587-1600 (2022)A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing.Z. Liang, D. Lv, C. Cui, H. Chen, W. He, W. Sheng, N. Jing, Z. Mao, and G. He. IEEE Trans. Very Large Scale Integr. Syst., 29 (2): 307-320 (2021)Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology.J. Guo, L. Zhu, W. Liu, H. Huang, S. Liu, T. Wang, L. Xiao, and Z. Mao. IEEE Trans. Very Large Scale Integr. Syst., 25 (5): 1593-1600 (2017)Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling.Z. Zhao, W. Sheng, Q. Wang, W. Yin, P. Ye, J. Li, and Z. Mao. IEEE Trans. Parallel Distributed Syst., 31 (9): 2201-2219 (2020)

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Disambiguation of "Mao, Zhigang"

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A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.

Please choose a person to relate this publication to

Zhigang Shen

Zhigang Zhang

Zhigang Zhang

Zhigang Gao

Zhigang Zhang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Mao, Zhigang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.

Please choose a person to relate this publication to

Zhigang Shen

Zhigang Zhang

Zhigang Zhang

Zhigang Gao

Zhigang Zhang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator.