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Disambiguation of "Bertulessi, Luca"

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A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter.

, , , , , , , and . IEEE J. Solid State Circuits, 57 (2): 505-517 (2022)

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Luca Rizzini

Luca Tranchini

Luca Tuninetti

Alfonz Luca

Marcello Lucà

 

Other publications of authors with the same name

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2466-2477 (September 2023)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS., , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3493-3502 (2019)A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter., , , , , , , and . IEEE J. Solid State Circuits, 57 (2): 505-517 (2022)A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters., , , , , , , , and . NEWCAS, page 20-24. IEEE, (2022)A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 58 (3): 634-646 (March 2023)A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 57 (6): 1723-1735 (2022)A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations., , , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3645-3649 (2022)A Background Calibration Technique to Control the Bandwidth of Digital PLLs., , , , , and . IEEE J. Solid State Circuits, 53 (11): 3243-3255 (2018)