Author of the publication

Dynamic addressing memory arrays with physical locality.

, , , , and . MICRO, page 161-170. ACM/IEEE Computer Society, (2002)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Trading Off Cache Capacity for Low-Voltage Operation., , , , , and . IEEE Micro, 29 (1): 96-103 (2009)O2MD²: A New Post-Quantum Cryptosystem With One-to-Many Distributed Key Management Based on Prime Modulo Double Encapsulation., , , and . IEEE Access, (2021)Adaptive Cache Design to Enable Reliable Low-Voltage Operation., , , , and . IEEE Trans. Computers, 60 (1): 50-63 (2011)Reducing cache and TLB power by exploiting memory region and privilege level semantics., , , , , , and . J. Syst. Archit., 59 (6): 279-295 (2013)Design, implementation, and verification of active cache emulator (ACE)., , and . FPGA, page 63-72. ACM, (2006)A Reliable, Low-Cost, Low-Energy Physically Unclonable Function Circuit Through Effective Filtering., , , , , and . VLSI-DAT, page 1-4. IEEE, (2019)Trading off Cache Capacity for Reliability to Enable Low Voltage Operation., , , , , and . ISCA, page 203-214. IEEE Computer Society, (2008)CompAcc: Efficient Hardware Realization for Processing Compressed Neural Networks Using Accumulator Arrays., , , , , and . A-SSCC, page 1-4. IEEE, (2020)Advances of the Counterflow Pipeline Microarchitecture., , and . HPCA, page 230-236. IEEE Computer Society, (1997)Distributed hardware matcher framework for SoC survivability., and . DATE, page 305-310. IEEE, (2011)