( en | de | ru )

 

Disambiguation of "Tanzawa, Toru"

Author of the publication

copydeleteadd this publication to your clipboard
Charge Pumps for Ultra-Low-Power Applications: Analysis, Design, and New Solutions.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2895-2901 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ahmet Refah Torun

 

Other publications of authors with the same name

Optimization of word-line booster circuits for low-voltage flash memories., and . IEEE J. Solid State Circuits, 34 (8): 1091-1098 (1999)A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)A Circuit Analysis of Pre-Emphasis Pulses for RC Delay Lines., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (6): 912-926 (2021)On-chip switched-capacitor DC-DC converter in memory technology: State of the art and challenges.. ECCTD, page 1-4. IEEE, (2017)A process- and temperature-tolerant power-on reset circuit with a flexible detection level higher than the bandgap voltage.. ISCAS, page 2302-2305. IEEE, (2008)On the Output Impedance and an Output Current-Power Efficiency Relationship of Dickson Charge Pump Circuits.. IEEE Trans. Circuits Syst. II Express Briefs, 65-II (11): 1664-1667 (2018)Linear distribution of capacitance in Dickson charge pumps to reduce rise time., , , and . I. J. Circuit Theory and Applications, 48 (4): 555-566 (2020)A multipage cell architecture for high-speed programming multilevel NAND flash memories., , and . IEEE J. Solid State Circuits, 33 (8): 1228-1238 (1998)Design of a sense circuit for low-voltage flash memories., , , and . IEEE J. Solid State Circuits, 35 (10): 1415-1421 (2000)Design Considerations on Power, Performance, Reliability and Yield in 3D NAND Technology.. IEICE Trans. Electron., 101-C (1): 78-81 (2018)