( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
CAD at the Design-Manufacturing Interface.

, , , , , и . DAC, стр. 321-326. ACM Press, (1997)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Witold Jeszke

Witold Lesniak

Witold Ostapowicz

Witold Zenk

Witold Slowinski

 

Другие публикации лиц с тем же именем

IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology., , и . MIXDES, стр. 334-338. IEEE, (2015)A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (2): 151-162 (1999)Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement., , , , , и . Microelectron. Reliab., 41 (12): 2023-2040 (2001)Hierarchical test generation for combinational circuits with real defects coverage., , , , , , и . Microelectron. Reliab., 42 (7): 1141-1149 (2002)Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology., , , и . DDECS, стр. 259-262. IEEE Computer Society, (2008)LC-VCO design automation tool for nanometer CMOS technology., , и . DDECS, стр. 68-73. IEEE, (2012)PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications., , и . DDECS, стр. 29-34. IEEE Computer Society, (2011)Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS., , и . DDECS, стр. 78-83. IEEE Computer Society, (2009)Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC., , , , , и . DSD, стр. 729-734. IEEE Computer Society, (2008)Yield Estimation of VLSI Circuits with Downscaled Layouts.. DFT, стр. 55-60. IEEE Computer Society, (1999)