Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.

K. Ueyoshi, K. Ando, K. Hirose, S. Takamaeda-Yamazaki, M. Hamada, T. Kuroda, and M. Motomura. IEEE J. Solid State Circuits, 54 (1): 186-196 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Masato Ishizaki

Masato Ikuta

Daniele Masato

Other publications of authors with the same name

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers.S. Jimbo, D. Okonogi, K. Ando, T. Chu, J. Yu, M. Motomura, and K. Kawamura. IEICE Trans. Inf. Syst., 105-D (12): 2019-2031 (December 2022)Advanced Devices and Architectures.M. Motomura, M. Hariyama, and M. Watanabe. Principles and Structures of FPGAs, Springer, (2018)Wrapper-based bus implementation techniques for performance improvement and cost reduction.K. Anjo, A. Okamura, and M. Motomura. IEEE J. Solid State Circuits, 39 (5): 804-817 (2004)Cache-processor coupling: a fast and wide on-chip data cache design.M. Motomura, T. Inoue, H. Yamada, and A. Konagaya. IEEE J. Solid State Circuits, 30 (4): 375-382 (April 1995)New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic.M. Méribout, and M. Motomura. J. Syst. Archit., 48 (8-10): 285-310 (2003)F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.M. Chang, J. Deguchi, V. De, M. Motomura, S. Shiratake, and M. Verhelst. ISSCC, page 506-508. IEEE, (2017)Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner.K. Ando, J. Yu, K. Hirose, H. Nakahara, K. Kawamura, T. Chu, and M. Motomura. HCS, page 1-21. IEEE, (2021)A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations.M. Yasunaga, J. Suzuki, M. Watanabe, K. Kawamura, T. Chu, J. Yu, and M. Motomura. MCSoC, page 478-485. IEEE, (2023)An Embedded DRAM-FPGA Chip with Instantaneous Logic Reconfiguration.M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, and M. Yamashina. FCCM, page 264-266. IEEE Computer Society, (1998)Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces.T. Asai, M. Mori, T. Itou, Y. Take, M. Ikebe, T. Kuroda, and M. Motomura. ESSCIRC, page 105-108. IEEE, (2016)

BibSonomy

Disambiguation of "Motomura, Masato"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.

Please choose a person to relate this publication to

Masato Ishizaki

Masato Ikuta

Daniele Masato

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Motomura, Masato"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.

Please choose a person to relate this publication to

Masato Ishizaki

Masato Ikuta

Daniele Masato

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS.