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Disambiguation of "Deguchi, Jun"

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F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems.

, , , , , and . ISSCC, page 506-508. IEEE, (2017)

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Masahisa Deguchi

Jun Jun Lu

Jun Yang

Jun Yang

Jun Li

 

Other publications of authors with the same name

Session 4 overview: Imagers., , and . ISSCC, page 64-65. IEEE, (2017)A 1.4Mpixel CMOS image sensor with multiple row-rescan based data sampling for optical camera communication., , , , , , , and . A-SSCC, page 17-20. IEEE, (2014)A fully integrated 2×1 dual-band direct-conversion transceiver with dual-mode fractional divider and noise-shaping TIA for mobile WiMAX SoC in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 456-457. IEEE, (2010)A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 2 other author(s). ISSCC, page 478-480. IEEE, (2019)FPGA-based CNN Processor with Filter-Wise-Optimized Bit Precision., , , , , and . A-SSCC, page 47-50. IEEE, (2018)Quantization Strategy for Pareto-optimally Low-cost and Accurate CNN., , , , , , and . AICAS, page 1-4. IEEE, (2021)RaLLe: A Framework for Developing and Evaluating Retrieval-Augmented Large Language Models., , , , , , and . EMNLP (Demos), page 52-69. Association for Computational Linguistics, (2023)A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 57 (5): 1517-1526 (2022)Introduction to the Special Section on the 2021 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 57 (1): 3-5 (2022)Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology., , , and . A-SSCC, page 25-28. IEEE, (2016)