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Disambiguation of "Hsieh, Min-Han"

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A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique.

, , , , , , and . ISCAS, page 1423-1426. IEEE, (2011)

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Liang-Han Hsieh

Chi-Min Hsieh

Han Min Woo

Min-chü Han

Marianne Min-Jean Hsieh

 

Other publications of authors with the same name

System-impact analysis of a large-scale offshore wind farm connected to Taiwan power system., , , , and . IAS, page 1-6. IEEE, (2013)A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS., , , and . IEEE J. Solid State Circuits, 51 (2): 412-427 (2016)A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology., , , , and . ISCAS, page 1404-1407. IEEE, (2013)A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique., , , , , , and . ISCAS, page 1423-1426. IEEE, (2011)A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS., , , and . ISSCC, page 244-246. IEEE, (2012)An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (8): 1644-1655 (2012)A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme., , , , , and . ISCAS, page 2393-2396. IEEE, (2015)A 12 Gb/s chip-to-chip AC coupled transceiver., , , , , , and . ISCAS, page 1692-1695. IEEE, (2011)A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique., , , , , and . ISCAS, page 553-556. IEEE, (2015)An at-speed self-testable technique for the high speed domino adder., , , , , and . CICC, page 1-4. IEEE, (2011)