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High density 3D integration by pre-applied Inter Chip Fill., , , , , , , , and . 3DIC, page 1-5. IEEE, (2010)Combination between the nonlinear finite element analyses and the strain measurement using the digital image correlation for a new 3D SIC package., , , , , , , , and . 3DIC, page 1-6. IEEE, (2011)Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration., , , , , , , , and . 3DIC, page 1-7. IEEE, (2011)Thermal design guideline and new cooling solution for a three-dimensional (3D) chip stack., , , , , , , , , and 1 other author(s). 3DIC, page 1-8. IEEE, (2013)Thermo-mechanical evaluation of 3D packages., , , , , , and . 3DIC, page 1-4. IEEE, (2013)Semiconductor Packaging Revolution in the Era of Chiplets.. ICICDT, page ix. IEEE, (2023)Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration., , , , , , and . 3DIC, page TS8.3.1-TS8.3.5. IEEE, (2015)Solder joint reliability evaluation of chip scale package using a modified Coffin-Manson equation., , and . Microelectron. Reliab., 44 (2): 269-274 (2004)Semiconductor Packaging Revolution in the Era of Chiplets : Keynote 1.. ITC-Asia, page 1. IEEE, (2023)Molecular Inverse-Design Platform for Material Industries., , , , , , , , , and 10 other author(s). KDD, page 2961-2969. ACM, (2020)