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An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

K. Zhou, C. Zhao, J. Fang, J. Jiang, D. Chen, Y. Huang, M. e Jing, J. Han, H. Tian, X. Xiong, Q. Liu, X. Xue, and X. Zeng. IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2932-2936 (2021)

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Xianjun Xiong

Xiong Qi

Guangwei Xiong

Lixiang Xiong

Ning Xiong

Other publications of authors with the same name

TPNoC: An Efficient Topology Reconfigurable NoC Generator.J. Yu, F. Yang, X. Yi, C. Chen, J. Tao, D. Xu, X. Xiong, and H. Yang. ACM Great Lakes Symposium on VLSI, page 77-82. ACM, (2023)NNASIM: An Efficient Event-Driven Simulator for DNN Accelerators with Accurate Timing and Area Models.X. Yi, J. Yu, Z. Wu, X. Xiong, D. Xu, C. Chen, J. Tao, and F. Yang. ISCAS, page 2806-2810. IEEE, (2022)A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications.D. Chen, Z. Guo, J. Fang, C. Zhao, J. Jiang, K. Zhou, H. Tian, X. Xiong, X. Xue, and X. Zeng. IEEE Trans. Circuits Syst. II Express Briefs, 70 (1): 276-280 (2023)A Design of 16TOPS Efficient GEMM Module in Deep Learning Accelerator.G. Lu, D. Xu, N. Wang, X. Zhang, D. Zhen, H. Lei, Y. Bai, D. Kong, H. Ruan, Z. Chi and 2 other author(s). ICTA, page 59-60. IEEE, (2020)An Automated Compiler for RISC-V Based DNN Accelerator.Z. Wu, W. Xie, X. Yi, H. Yang, R. Pu, X. Xiong, H. Yao, C. Chen, J. Tao, and F. Yang. ISCAS, page 3097-3101. IEEE, (2022)An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices.Z. Guo, D. Chen, C. Zhao, J. Fang, J. Jiang, Y. Liu, H. Tian, X. Xiong, K. Zhou, X. Xue and 2 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 70 (7): 2645-2649 (July 2023)A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization.X. Jia, H. Zhu, Y. Wang, J. Zhang, F. Lin, X. Xiong, D. Xu, C. Chen, and Q. Liu. ISCAS, page 2816-2820. IEEE, (2022)A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.Y. Lin, Y. Wang, X. Hu, J. Feng, G. Wen, X. Xiong, H. Tian, and Y. Xie. ASICON, page 1-4. IEEE, (2021)An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.K. Zhou, C. Zhao, J. Fang, J. Jiang, D. Chen, Y. Huang, M. e Jing, J. Han, H. Tian, X. Xiong and 3 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2932-2936 (2021)Graph Representation Learning for Microarchitecture Design Space Exploration.X. Yi, J. Lu, X. Xiong, D. Xu, L. Shang, and F. Yang. DAC, page 1-6. IEEE, (2023)

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Disambiguation of "Xiong, Xiankui"

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DOI
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An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

Please choose a person to relate this publication to

Xianjun Xiong

Xiong Qi

Guangwei Xiong

Lixiang Xiong

Ning Xiong

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xiong, Xiankui"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.

Please choose a person to relate this publication to

Xianjun Xiong

Xiong Qi

Guangwei Xiong

Lixiang Xiong

Ning Xiong

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
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APA
Chicago
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An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications.