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Disambiguation of "Lien, Nan-Chun"

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A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist.

, , , , , , , , , , , , , , , , , , and . ISCAS, page 1468-1471. IEEE, (2013)

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Chun-Nan Kuo

Lien

Lien Wang

Shi Nan

Nan Meng

 

Other publications of authors with the same name

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , and 9 other author(s). SoCC, page 197-200. IEEE, (2011)An all-digital bit transistor characterization scheme for CMOS 6T SRAM array., , , , , , , , , and . ISCAS, page 2485-2488. IEEE, (2012)Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM., , , , , , , , , and 1 other author(s). APCCAS, page 116-119. IEEE, (2012)A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 56 (9): 2817-2831 (2021)High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder., , , , , , , , , and 6 other author(s). ISCAS, page 1831-1834. IEEE, (2012)An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array., , , , , , , , , and 1 other author(s). VLSI-DAT, page 1-4. IEEE, (2012)Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array., , , , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2012)A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist., , , , , , , , , and 3 other author(s). SoCC, page 218-223. IEEE, (2012)15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips., , , , , , , , , and 17 other author(s). ISSCC, page 246-248. IEEE, (2020)A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist., , , , , , , , , and 9 other author(s). ISCAS, page 1468-1471. IEEE, (2013)