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S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC.

C. Erdmann, B. Verbruggen, B. Vaz, R. Pelliconi, J. McGrath, R. Kinnerk, R. Torre, J. O'Dwyer, P. Lynch, P. Kelly, P. Lim, D. Breathnach, and B. Farley. VLSI Circuits, page 219-220. IEEE, (2018)

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Martino La Torre

Hector la Torre

Luis La Torre

Silvia Eunice Gutiérrez de la Torre Julius-Maximilians-Universität Würzburg

Annabel la Torre Cevallos

Other publications of authors with the same name

A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET.B. Vaz, B. Verbruggen, C. Erdmann, D. Collins, J. McGrath, A. Boumaalif, E. Cullen, D. Walsh, A. Morgado, C. Mesadri and 10 other author(s). VLSI Circuits, page 99-100. IEEE, (2018)A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC.C. Erdmann, B. Verbruggen, B. Vaz, R. Pelliconi, J. McGrath, R. Kinnerk, R. Torre, J. O'Dwyer, P. Lynch, P. Kelly and 3 other author(s). VLSI Circuits, page 219-220. IEEE, (2018)6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters.C. Erdmann, D. Lowney, A. Lynam, A. Keady, J. McGrath, E. Cullen, D. Breathnach, D. Keane, P. Lynch, M. Torre and 5 other author(s). ISSCC, page 120-121. IEEE, (2014)A Heterogeneous 3D-IC Consisting of Two 28 nm FPGA Die and 32 Reconfigurable High-Performance Data Converters.C. Erdmann, D. Lowney, A. Lynam, A. Keady, J. McGrath, E. Cullen, D. Breathnach, D. Keane, P. Lynch, M. Torre and 5 other author(s). IEEE J. Solid State Circuits, 50 (1): 258-269 (2015)16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC.B. Vaz, A. Lynam, B. Verbruggen, A. Laraba, C. Mesadri, A. Boumaalif, J. McGrath, U. Kamath, R. Torre, A. Manlapat and 3 other author(s). ISSCC, page 276-277. IEEE, (2017)

BibSonomy

Disambiguation of "Torre, Ronnie De La"