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Disambiguation of "Varma, B. Sharat Chandra"

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Configurable Architectures for Multi-Mode Floating Point Adders.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2079-2090 (2015)

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Sharat Chikkerur

Nitin Varma

Sarvesh Varma

Gyaneshwar Varma

Sudhir Varma

 

Other publications of authors with the same name

High-throughput cellular imaging with high-speed asymmetric-detection time-stretch optical microscopy under FPGA platform., , , , , , , , and . ReConFig, page 1-6. IEEE, (2016)Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAs., , and . VLSID, page 306-311. IEEE Computer Society, (2014)Configurable Architectures for Multi-Mode Floating Point Adders., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2079-2090 (2015)FAssem: FPGA Based Acceleration of De Novo Genome Assembly., , , and . FCCM, page 173-176. IEEE Computer Society, (2013)Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA., , , , , , , and . FPT, page 261-264. IEEE, (2016)Architecture for Dual-Mode Quadruple Precision Floating Point Adder., , and . ISVLSI, page 249-254. IEEE Computer Society, (2015)Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs., , and . VLSI Design, page 92-97. IEEE Computer Society, (2013)Hardware acceleration of de novo genome assembly., , , and . Int. J. Embed. Syst., 9 (1): 74-89 (2017)High Level Design Approach to Accelerate De Novo Genome Assembly Using FPGAs., , and . DSD, page 66-73. IEEE Computer Society, (2014)