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Disambiguation of "Jaiswal, Manish Kumar"

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Configurable Architectures for Multi-Mode Floating Point Adders.

, , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2079-2090 (2015)

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Manish Kumar

Manoj Kumar Jaiswal

Ashok Kumar Jaiswal

Manish Kumar Aneja

Himjyot Jaiswal

 

Other publications of authors with the same name

Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (7): 521-525 (2014)Universal number posit arithmetic generator on FPGA., and . DATE, page 1159-1162. IEEE, (2018)Dual-mode double precision / two-parallel single precision floating point multiplier architecture., and . VLSI-SoC, page 213-218. IEEE, (2015)Efficient Implementation of IEEE Double Precision Floating-Point Multiplier on FPGA., and . ICIIS, page 1-4. IEEE, (2008)Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA., , , , , , , and . FPT, page 261-264. IEEE, (2016)Architecture for Dual-Mode Quadruple Precision Floating Point Adder., , and . ISVLSI, page 249-254. IEEE Computer Society, (2015)Architecture for quadruple precision floating point division with multi-precision support., and . ASAP, page 239-240. IEEE Computer Society, (2016)E-TCAM: An Efficient SRAM-Based Architecture for TCAM., , and . Circuits Syst. Signal Process., 33 (10): 3123-3144 (2014)Configurable Architectures for Multi-Mode Floating Point Adders., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (8): 2079-2090 (2015)Dual-mode double precision division architecture., and . MWSCAS, page 1-4. IEEE, (2016)