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Interactive presentation: Improving the fault tolerance of nanometric PLA designs.

, , , , and . DATE, page 570-575. EDA Consortium, San Jose, CA, USA, (2007)

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Complete nanowire crossbar framework optimized for the multi-spacer patterning technique., , , and . CASES, page 11-16. ACM, (2009)Interactive presentation: Improving the fault tolerance of nanometric PLA designs., , , , and . DATE, page 570-575. EDA Consortium, San Jose, CA, USA, (2007)Programmable logic circuits based on ambipolar CNFET., , , and . DAC, page 339-340. ACM, (2008)Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (11): 2053-2067 (2008)Synthesis of regular computational fabrics with ambipolar CNTFET technology., , , and . ICECS, page 70-73. IEEE, (2010)Using TSVs for thermal mitigation in 3D circuits: Wish and truth., , , , , , , , , and 1 other author(s). 3DIC, page 1-8. IEEE, (2014)Characterization of memristive Poly-Si Nanowires via empirical physical modelling., , , , and . ISCAS, page 1675-1678. IEEE, (2010)Design aspects of carry lookahead adders with vertically-stacked nanowire transistors., , , and . ISCAS, page 1715-1718. IEEE, (2010)Evaluation of a crossbar multiplexer in a lithography-based nanowire technology., , , and . ISCAS, page 2930-2933. IEEE, (2011)Ultra-fine grain FPGAs: A granularity study., , , and . NANOARCH, page 9-15. IEEE Computer Society, (2011)