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Interactive presentation: Improving the fault tolerance of nanometric PLA designs.

, , , , and . DATE, page 570-575. EDA Consortium, San Jose, CA, USA, (2007)

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3.5-D integration: A case study., , , , and . ISCAS, page 2087-2090. IEEE, (2013)A Self-Contained System With CNTs-Based Biosensors for Cell Culture Monitoring., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (4): 658-671 (2012)Hierarchical Thermal Management Policy for High-Performance 3D Systems With Liquid Cooling., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 88-101 (2011)PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays., and . DAC, page 530-537. ACM/IEEE, (1983)High-Level Synthesis of Digital Circuits.. Advances in Computers, (1993)Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache., , , and . ISQED, page 163-170. IEEE, (2014)Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting., , , , , and . IEEE Trans. Computers, 48 (8): 769-779 (1999)A Sound and Complete Axiomatization of Majority-n Logic., , , and . IEEE Trans. Computers, 65 (9): 2889-2895 (2016)Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms., , , , and . DAC, page 247-252. ACM Press, (1999)Design aspects of carry lookahead adders with vertically-stacked nanowire transistors., , , and . ISCAS, page 1715-1718. IEEE, (2010)