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Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (3): 445-456 (2018)

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Morphable Structures for Reconfigurable Instruction Set Processors., , and . Asia-Pacific Computer Systems Architecture Conference, volume 3740 of Lecture Notes in Computer Science, page 450-463. Springer, (2005)The Art of Guessing in Combined Side-Channel Collision Attacks., , and . IACR Cryptology ePrint Archive, (2019)Dynamic skewed tree for fast memory integrity verification., , and . DATE, page 642-647. IEEE, (2018)Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration., , and . ReCoSoC, page 1-8. IEEE, (2012)SNR-Centric Power Trace Extractors for Side-Channel Attacks., , , , , and . IACR Cryptology ePrint Archive, (2019)Lowering dynamic power in stream-based harris corner detection architecture., , and . FPT, page 176-182. IEEE, (2017)Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs., , and . IEEE Trans. Computers, 60 (5): 680-692 (2011)Stereo based ROIs generation for detecting pedestrians in close proximity., , and . ITSC, page 1929-1934. IEEE, (2014)Shortest Partial Path First Algorithm for Reconfigurable Processor Array with Faults., , , and . Trustcom/BigDataSE/ISPA, page 1198-1203. IEEE, (2016)Multiple-Choice Hardware/Software Partitioning for Tree Task-Graph on MPSoC., , , and . Comput. J., 63 (5): 688-700 (2020)