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Disambiguation of "Nedovic, Nikola"

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Comparative analysis of double-edge versus single-edge triggered clocked storage elements.

, , and . ISCAS (5), page 105-108. IEEE, (2002)

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Nikola Brzovic

Nikola Pantscheff

Nikola Sirakoff

Nikola Schoofs

Nikola Stiasni

 

Other publications of authors with the same name

A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . ISSCC, page 224-598. IEEE, (2007)Conditional pre-charge techniques for power-efficient dual-edge clocking., , and . ISLPED, page 56-59. ACM, (2002)A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 724-732. Springer, (2005)Timing Characterization of Dual-edge Triggered Flip-flops., , and . ICCD, page 538-541. IEEE Computer Society, (2001)16.4 High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking., , , , , , and . ISSCC, page 302-304. IEEE, (2024)Comparative analysis of double-edge versus single-edge triggered clocked storage elements., , and . ISCAS (5), page 105-108. IEEE, (2002)Conditional techniques for low power consumption flip-flops., , and . ICECS, page 803-806. IEEE, (2001)A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET., , , , , , , , , and 1 other author(s). CICC, page 1-4. IEEE, (2019)Hybrid latch Flip-Flop with Improved Power Efficiency., and . SBCCI, page 211-215. IEEE Computer Society, (2000)An FLL-Based Clock Glitch Detector for Security Circuits in a 5nm FINFET Process., , , , , and . VLSI Technology and Circuits, page 146-147. IEEE, (2022)