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A Trojan-invalidating Circuit Based on Signal Transitions and Its FPGA Implementation., , and . ISCAS, page 1-5. IEEE, (2018)An Effective Stochastic Number Duplicator and Its Evaluations Using Composite Arithmetic Circuits., , , and . IOLTS, page 53-56. IEEE, (2018)A robust scan-based side-channel attack method against HMAC-SHA-256 circuits., , and . ICCE-Berlin, page 79-84. IEEE, (2017)Area/delay estimation for digital signal processor cores., , , , and . ASP-DAC, page 156-161. ACM, (2001)An Incremental Placement and Global Routing Algorithm for Field-Programmable Gate Arrays., , , and . ASP-DAC, page 519-526. IEEE, (1998)A process-variation-aware multi-scenario high-level synthesis algorithm for distributed-register architectures., , , and . SoCC, page 7-12. IEEE, (2015)A delay variation and floorplan aware high-level synthesis algorithm with body biasing., , , and . ISQED, page 75-80. IEEE, (2016)A parallel LSI architecture for LDPC decoder improving message-passing schedule., , , , and . ISCAS, IEEE, (2006)Energy-efficient high-level synthesis for HDR architectures with clock gating., , and . ISOCC, page 135-138. IEEE, (2012)A visible corner-landmark based route finding algorithm for pedestrian navigation., , , , and . GCCE, page 601-602. IEEE, (2015)