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CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.

, , , , and . ASYNC, page 62-72. IEEE Computer Society, (2000)

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Distributed Diagnosis of Interconnections in SoC and MCM Designs., , and . J. Electron. Test., 20 (3): 291-307 (2004)DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor., , , , , , and . ITC, page 1-10. IEEE Computer Society, (2008)A distributed BIST technique for diagnosis of MCM interconnections., , and . ITC, page 214-221. IEEE Computer Society, (1998)Synthesis of BIST hardware for performance testing of MCM interconnections., , and . ICCAD, page 69-73. ACM / IEEE Computer Society, (1998)A Scalable, Low Cost Design-for-Test Architecture for UltraSPARCTM Chip Multi-Processors., , , , and . ITC, page 726-735. IEEE Computer Society, (2002)Single-probe traversal optimization for testing of MCM substrate interconnections., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (8): 1178-1191 (1999)Optimal single probe traversal algorithm for testing of MCM substrat., , and . ICCD, page 396-401. IEEE Computer Society, (1996)CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder., , , , and . ASYNC, page 62-72. IEEE Computer Society, (2000)Switching activity generation with automated BIST synthesis forperformance testing of interconnects., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (9): 1143-1158 (2001)