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CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder.

, , , , and . ASYNC, page 62-72. IEEE Computer Society, (2000)

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Relative timing asynchronous design., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 129-140 (2003)Relative Timing., , and . ASYNC, page 208-218. IEEE Computer Society, (1999)RAPPID: An Asynchronous Instruction Length Decoder., , , , , , , , , and . ASYNC, page 60-70. IEEE Computer Society, (1999)CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder., , , , and . ASYNC, page 62-72. IEEE Computer Society, (2000)CAD Directions for High Performance Asynchronous Circuits., , , , , , and . DAC, page 116-121. ACM Press, (1999)Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits., , , , , , , and . ASYNC, page 80-. IEEE Computer Society, (1998)An asynchronous instruction length decoder., , , , , , , , and . IEEE J. Solid State Circuits, 36 (2): 217-228 (2001)Coordinated transformations for high-level synthesis of high performance microprocessor blocks., , , , , , , and . DAC, page 898-903. ACM, (2002)