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Gate Leakage Impact on Full Open Defects in Interconnect Lines., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)ITC 2003 Roundtable: Design for Manufacturability., , , , and . IEEE Des. Test Comput., 21 (2): 144-156 (2004)Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model., , , , , and . VTS, page 345-350. IEEE Computer Society, (2003)Memory Testing Under Different Stress Conditions: An Industrial Evaluation., , , , , and . DATE, page 438-443. IEEE Computer Society, (2005)Memory Testing Under Different Stress Conditions: An Industrial Evaluation, , , , , and . CoRR, (2007)Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1911-1922 (2011)Memory testing improvements through different stress conditions., , , , , and . ESSCIRC, page 299-302. IEEE, (2005)Modeling Power Supply Noise in Delay Testing., , , , , , , , and . IEEE Des. Test Comput., 24 (3): 226-234 (2007)Diagnosis of full open defects in interconnect lines with fan-out., , , , , and . European Test Symposium, page 233-238. IEEE Computer Society, (2010)Systematic Defects in Deep Sub-Micron Technologies., , , , and . ITC, page 290-299. IEEE Computer Society, (2004)