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Efficient Grouping of Fail Chips for Volume Yield Diagnostics., , , and . VLSI Design, page 97-102. IEEE Computer Society, (2009)Mixed-Signal Test., and . VLSI Design, page 285-288. IEEE Computer Society, (1998)Memory Testing Under Different Stress Conditions: An Industrial Evaluation., , , , , and . DATE, page 438-443. IEEE Computer Society, (2005)Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model., , , , , and . VTS, page 345-350. IEEE Computer Society, (2003)Memory Testing Under Different Stress Conditions: An Industrial Evaluation, , , , , and . CoRR, (2007)NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (5): 809-813 (2012)Memory testing improvements through different stress conditions., , , , , and . ESSCIRC, page 299-302. IEEE, (2005)Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects., , , , and . ITC, page 1-10. IEEE Computer Society, (2007)A genetic algorithm-based circuit partitioner for MCMs., , and . Microprocess. Microprogramming, 41 (1): 83-96 (1995)Power Supply Noise in Delay Testing., , , , , , , and . ITC, page 1-10. IEEE Computer Society, (2006)