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Gate Leakage Impact on Full Open Defects in Interconnect Lines.

, , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)

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Stefan Dominik Eichenberger

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Christian Eichenberger

Christoph Eichenberger

Patrick Eichenberger

 

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Gate Leakage Impact on Full Open Defects in Interconnect Lines., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (12): 2209-2220 (2011)ITC 2003 Roundtable: Design for Manufacturability., , , , и . IEEE Des. Test Comput., 21 (2): 144-156 (2004)Memory Testing Under Different Stress Conditions: An Industrial Evaluation., , , , , и . DATE, стр. 438-443. IEEE Computer Society, (2005)Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model., , , , , и . VTS, стр. 345-350. IEEE Computer Society, (2003)Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 30 (12): 1911-1922 (2011)Memory Testing Under Different Stress Conditions: An Industrial Evaluation, , , , , и . CoRR, (2007)Memory testing improvements through different stress conditions., , , , , и . ESSCIRC, стр. 299-302. IEEE, (2005)Diagnosis of full open defects in interconnect lines with fan-out., , , , , и . European Test Symposium, стр. 233-238. IEEE Computer Society, (2010)Modeling Power Supply Noise in Delay Testing., , , , , , , , и . IEEE Des. Test Comput., 24 (3): 226-234 (2007)Systematic Defects in Deep Sub-Micron Technologies., , , , и . ITC, стр. 290-299. IEEE Computer Society, (2004)