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Disambiguation of "Yang, Ping-Lin"

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A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB.

, , , , , , and . CICC, page 1-4. IEEE, (2013)

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Ping Yang

Ping Yang

Lin Yang

Lin Yang

Yang Lin

 

Other publications of authors with the same name

Making split-fabrication more secure., and . ICCAD, page 91. ACM, (2016)A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC., , , , , , , and . CICC, page 1-4. IEEE, (2014)A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB., , , , , , and . CICC, page 1-4. IEEE, (2013)Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology., , , , , , , , and . CICC, page 1-3. IEEE, (2015)A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2014)A 4-GHz universal high-frequency on-chip testing platform for IP validation., , , , , , , and . VTS, page 1-6. IEEE Computer Society, (2014)High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators., and . IEEE Trans. Very Large Scale Integr. Syst., 26 (7): 1209-1222 (2018)A fast, fully verifiable, and hardware predictable ASIC design methodology., and . ICCD, page 364-367. IEEE Computer Society, (2016)