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Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit.

, , , , , , and . Microelectron. J., 46 (12): 1106-1113 (2015)

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Thermal impact of extreme die thinning in bump-bonded three-dimensional integrated circuits., , , , , and . Microelectron. Reliab., (2017)Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels., , , , , , , , , and 1 other author(s). IET Circuits Devices Syst., 6 (1): 35-44 (2012)Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration., , , and . ACM Trans. Design Autom. Electr. Syst., 16 (1): 5:1-5:25 (2010)Exploring compromises among timing, power and temperature in three-dimensional integrated circuits., , , , , , and . DAC, page 997-1002. ACM, (2006)Junction-level thermal extraction and simulation of 3DICs., , , , , and . 3DIC, page 1-7. IEEE, (2009)Inter-die signaling in three dimensional integrated circuits., , , and . CICC, page 655-658. IEEE, (2008)Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High Definition Power Blurring., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (5): 676-689 (2012)Investigation of effects of metalization on heat spreading in bump-bonded 3D systems., , and . 3DIC, page TS8.30.1-TS8.30.4. IEEE, (2015)Impact of thinning stacked dies on the thermal resistance of bump-bonded three-dimensional integrated circuits., , , , , and . Microelectron. Reliab., (2016)Design and CAD for 3D integrated circuits., , , , , , , , , and 2 other author(s). DAC, page 668-673. ACM, (2008)