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Fully on-chip clock jitter and skew measurement scheme via incoherent subsampling.

, , , , and . Microelectron. J., (2020)

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A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs., , , , , , , and . ISCAS, page 129-132. IEEE, (2013)A CMOS Differential Difference Amplifier with Reduced Nonlinearity Error of Interpolation for Interpolating ADCs., , and . APCCAS, page 9-12. IEEE, (2006)Design of Low-Power High-Performance FinFET Standard Cells., , , , , and . CSSP, 37 (5): 1789-1806 (2018)Balance Differential Coherent Bit Synchronization Algorithm for GNSS Receiver., , , and . IEICE Trans. Commun., 98-B (6): 1133-1140 (2015)Designing a 3D Graphics Processor for Mobile Applications., , and . ASICON, page 1-4. IEEE, (2019)A Novel Polymorphic Gate Based Circuit Fingerprinting Technique., , , , , , and . ACM Great Lakes Symposium on VLSI, page 141-146. ACM, (2018)FPGA Implementation of Quantized Convolutional Neural Networks., , , , , and . ICCT, page 1605-1610. IEEE, (2019)Employing the mixed FBB/RBB in the design of FinFET logic gates., , , , , , and . ASICON, page 1-4. IEEE, (2015)A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications., , , , , , and . ASICON, page 1-4. IEEE, (2015)Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (10): 1922-1929 (2018)