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Disambiguation of "Gaitonde, Dinesh"

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Placement Strategies for 2.5D FPGA Fabric Architectures.

, , and . FPL, page 16-20. IEEE Computer Society, (2018)

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Dinesh Lathia

Dinesh Adhikary

Dinesh Thilakarathna

Dinesh Subramaniam

Dinesh Chandra Bhardwaj

 

Other publications of authors with the same name

Network-on-Chip Programmable Platform in VersalTM ACAP Architecture., , , , and . FPGA, page 212-221. ACM, (2019)Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs., , , , , , and . FCCM, page 133-143. IEEE, (2023)An overview of library characterization in semi-custom design., and . CICC, page 305-312. IEEE, (1998)Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture., , , and . FPGA, page 84-93. ACM, (2019)IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck., , , , and . ICCAD, page 1-9. IEEE, (2023)Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing., , , , and . FPGA, page 231. ACM, (2023)SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs., , and . FPT, page 118-125. IEEE, (2018)Versal Network-on-Chip (NoC)., , , , , , , and . Hot Interconnects, page 13-17. IEEE, (2019)Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network., , , and . FPGA, page 74-79. ACM, (2016)100% Visibility at MHz Speed: Efficient Soft Scan-Chain Insertion on AMD/Xilinx FPGAs., , and . ARC, volume 13569 of Lecture Notes in Computer Science, page 1-16. Springer, (2022)