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7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.

T. Tanaka, M. Helm, T. Vali, R. Ghodsi, K. Kawai, J. Park, S. Yamada, F. Pan, Y. Einaga, A. Ghalam, T. Tanzawa, J. Guo, T. Ichikawa, E. Yu, S. Tamada, T. Manabe, J. Kishimoto, Y. Oikawa, Y. Takashima, H. Kuge, M. Morooka, A. Mohammadzadeh, J. Kang, J. Tsai, E. Sirizotti, E. Lee, L. Vu, Y. Liu, H. Choi, K. Cheon, D. Song, D. Shin, J. Yun, M. Piccardi, K. Chan, Y. Luthra, D. Srinivasan, S. Deshmukh, K. Kavalipurapu, D. Nguyen, G. Gallo, S. Ramprasad, M. Luo, Q. Tang, M. Incarnati, A. Macerola, L. Pilolli, L. Santis, M. Rossini, V. Moschiano, G. Santin, B. Tronca, H. Lee, V. Patel, T. Pekny, A. Yip, N. Prabhu, P. Sule, T. Bemalkhedkar, K. Upadhyayula, and C. Jaramillo. ISSCC, page 142-144. IEEE, (2016)

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Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ulrike Torunsky

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Design of a sense circuit for low-voltage flash memories.T. Tanzawa, Y. Takano, T. Taura, and S. Atsumi. IEEE J. Solid State Circuits, 35 (10): 1415-1421 (2000)A multipage cell architecture for high-speed programming multilevel NAND flash memories.K. Takeuchi, T. Tanaka, and T. Tanzawa. IEEE J. Solid State Circuits, 33 (8): 1228-1238 (1998)A 2V 3.8µW Fully-Integrated Clocked AC-DC Charge Pump with 0.5V 500Ω Vibration Energy Harvester.H. Kawauchi, and T. Tanzawa. APCCAS, page 329-332. IEEE, (2019)High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories.T. Tanzawa, Y. Takano, K. Watanabe, and S. Atsumi. IEEE J. Solid State Circuits, 37 (10): 1318-1325 (2002)A CMOS bandgap reference circuit with sub-1-V operation.H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui. IEEE J. Solid State Circuits, 34 (5): 670-674 (1999)A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories.T. Tanzawa, T. Tanaka, S. Tamada, J. Kishimoto, S. Yamada, K. Kawai, T. Ichikawa, P. Chiang, and F. Roohparvar. ESSCIRC, page 106-109. IEEE, (2010)Dickson Charge Pump Circuit Design with Parasitic Resistance in Power Lines.T. Tanzawa. ISCAS, page 1763-1766. IEEE, (2009)An analytical model of AC-DC voltage multipliers.T. Tanzawa. ICECS, page 323-326. IEEE, (2014)Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors.T. Tanzawa, T. Murakoshi, T. Kamijo, T. Tanaka, J. McNeil, and K. Duesman. A-SSCC, page 165-168. IEEE, (2016)A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller.T. Tanzawa, A. Umezawa, T. Taura, H. Shiga, T. Hara, Y. Takano, T. Miyaba, N. Tokiwa, K. Watanabe, H. Watanabe and 4 other author(s). IEEE J. Solid State Circuits, 37 (11): 1485-1492 (2002)

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Disambiguation of "Tanzawa, Toru"

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7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.

Please choose a person to relate this publication to

Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ulrike Torunsky

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tanzawa, Toru"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.

Please choose a person to relate this publication to

Toru Nomura

Toru Matsuyama

Toru Kashima

Richard Heinrich Torunsky

Ulrike Torunsky

Other publications of authors with the same name

Disambiguation

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URL
DOI
BibTeX
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Chicago
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7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.